Technology Column

Isolation

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  Transistors are formed near the silicon wafer surface.
  To ensure that each transistor operates independently, it is necessary to prevent interference with other neighboring transistors. Therefore, the regions where transistors are to be formed are isolated. There are a number of methods for this isolation.
  The technique introduced here is called STI (Shallow Trench Isolation).

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  1. Oxide + nitride film growth

  First a silicon oxide film is formed by oxidizing a silicon wafer, and then a silicon nitride film is formed using the CVD method.

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  2. Resist pattern formation

  A resist pattern is formed.

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  3. Shallow trench formation

  Using the resist pattern as a mask, shallow trenches are cut by etching the silicon nitride film, silicon oxide film and silicon wafer.

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  4. Buried oxide film growth

  Trenches are filled by forming a thick silicon oxide film using the CVD method.

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  5. Buried oxide film polishing

  The surface is polished to remove the excess silicon oxide film, and the silicon oxide film is left only in the trenches.

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  6. Nitride film removal

  The silicon nitride film is removed using chemical treatment.

Well and channel formation

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  N-MOS transistors and p-MOS transistors are formed in a chip.
  Impurities appropriate for n-MOS transistors and p-MOS transistors are respectively implanted into the Si surface at appropriate concentrations in the regions where the transistors are to be formed (n-MOS: p-well, n-channel; p-MOS: n-well, p-channel). In the case where transistors with two or more different voltages and characteristics are made, impurity implantation of different dopants/dosages is additionally performed.
  Repeat “2-3. n-Channel” and “2-4. p-Channel.

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  1. p-Well

  A resist pattern is formed to cover the p-MOS area, and p-type impurities (e.g., boron (B)) are implanted in the n-MOS area.
  After implantation, the resist pattern is removed.

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  2. n-Well

  A resist pattern is formed to cover the n-MOS area, and n-type impurities (e.g., phosphorus (P)) are implanted in the p-MOS area.
  After implantation, the resist pattern is removed.

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  3. n-Channel

  A resist pattern is formed to cover the p-MOS area, and p-type impurities (e.g., boron (B)) are implanted in the n-MOS area.
  After implantation, the resist pattern is removed.

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  4. p-Channel

  A resist pattern is formed to cover the n-MOS area, and n-type impurities (e.g., arsenic (As)) are implanted in the p-MOS area.
  After implantation, the resist pattern is removed.

Gate oxidation and gate formation

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  This step is most important from the viewpoint of transistor characteristics.
  A gate oxide film greatly influences the performance and reliability of a transistor, and should therefore be a high-density thin film uniformly distributed over the wafer surface.
  Since the size of the gate formed may also greatly influence the performance of the transistor, strict dimensional control is necessary in both photo resist patterning and gate etching.
  Gate electrodes are formed of polysilicon (polycrystalline silicon) by CVD.

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  1. Gate oxidation

  The silicon surface is cleaned through chemical treatment, and then oxidized, forming a gate oxide film. The thickness and quality of this oxide film has a major effect on transistor performance and reliability, and thus it must be a thin, high-density film with a uniform distribution.

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  2. Polysilicon growth

  Polysilicon (polycrystalline silicon) to be the gate electrode is formed using the CVD method.

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  3. Formation of gate resist pattern

  Gate resist pattern is formed.

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  4. Gate etching

  Using the gate resist pattern as a mask, the gate is formed by etching the polysilicon and gate oxide film. After etching, the resist pattern is removed. Gate dimensions have a major effect on transistor performance, and thus strict dimensional control is needed in both gate resist patterning and gate etching.

LDD formation

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  To avoid adverse effects (such as slower operation speed) of transistor miniaturization, LDDs (Lightly Doped Drains, low density impurity drains) are formed.
  LDDs are also called extensions.
  N-LDD: N-type impurities (e.g., As+, P+) are implanted into n-MOS areas.
  P-LDD: P-type impurities (e.g., B+) are implanted into p-MOS areas.

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  1. n-LDD

  p-A resist pattern is formed to cover the p-MOS area, and n-type impurities (e.g., phosphorus (P), arsenic (As)) are implanted in the n-MOS area.
  After implantation, the resist pattern is removed.

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  2. p-LDD

  A resist pattern is formed to cover the n-MOS area, and p-type impurities (e.g., boron (B)) are implanted in the p-MOS area.
  After implantation, the resist pattern is removed.

Side wall spacers

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  An oxide film is formed only at side wall portions of gates for LDD formation (above mentioned) and salicidation (described below) of gates, sources, and drains.
  Side wall oxide film: A silicon oxide film is formed on the entire wafer surface. Side wall etching: Anisotropic etching (vertical direction) is performed on the oxide film so that the oxide film may be left only on gate side walls.

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  1. Side wall oxide film growth

  A silicon oxide film is formed using the CVD method over the entire surface of the silicon wafer.

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  2. Side wall etching

  If anisotropic etching is performed on the oxide film formed over the entire surface, it is possible to leave an oxide film only at the gate side walls. This sort of etching which does not use a resist pattern is called etching back.

Source/drain

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  Sources and drains are formed in n-MOS areas and p-MOS areas. The shapes of sources and drains are the same because usual transistors are symmetric. Which is a source or a drain is defined depending on the connection direction of the power supply.
  P-source/drain: P-type impurities (e.g., B+) are implanted into p-MOS areas.
  N-source/drain: N-type impurities (e.g., As+, P+) are implanted into n-MOS areas.

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  1. p-Source/drain

  A resist pattern is formed to cover the n-MOS area, and p-type impurities (e.g., boron (B)) are implanted in the p-MOS area.
  After implantation, the resist pattern is removed.

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  2. n-Source/drain

  A resist pattern is formed to cover the p-MOS area, and n-type impurities (e.g., phosphorus (P), arsenic (As)) are implanted in the n-MOS area.
  After implantation, the resist pattern is removed.

Silicide

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  Silicide (compound of silicon with metal) is formed on gates (polysilicon), sources and drains (Si wafer) as three MOS transistor electrodes in order to reduce contact resistance to metal wiring layers to be formed later. This silicide formation also has the effect of lowering the resistance of each electrode.
  Salicidation: A cobalt film is removed selectively by chemical etching (Self aligned silicide).

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  1. Cobalt film deposition (sputtering)

  A cobalt film is formed on the silicon wafer surface using the PVD method (sputtering). Metals other than cobalt used for silicide include nickel and titanium.

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  2. Cobalt silicide formation

  If a silicon wafer whose surface is coated with a cobalt film is heated, the part where the silicon and cobalt are in contact changes to cobalt silicide. Cobalt on the oxide film remains as cobalt.

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  3. Cobalt removal

  A cobalt film is removed selectively by chemical etching. Silicide remains on the gate, source and drain. Formation of silicide through self-alignment in this way is called salicide (self aligned silicide).

Dielectric film

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  The interconnect process for connecting elements such as transistors starts from this step.
  Dielectric film deposition: A thick silicon oxide film or the like is formed by CVD.
  Dielectric film polishing: The silicon oxide film is polished for the film planarization of the wafer surface.

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  1. Dielectric film formation

  A thick film of silicon oxide or similar material is formed on the silicon wafer surface using the CVD method.

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  2. Polishing of dielectric film

  Simply forming a dielectric film results in unevenness of the wafer surface and interferes with subsequent processing.
  The oxide film on the surface is polished to make it smooth.

Contact holes

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  To connect electrodes such as gates, sources, and drains of transistors to metal wiring layers, contact holes are made in the dielectric film and filled with W (tungsten).
  Plug-tungsten filling: Tungsten is deposited in contact holes.
  Plug-tungsten polishing: The surface is polished to remove excess tungsten and leave tungsten only in the contact holes.

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  1. Formation of contact hole resist pattern

  A resist pattern for contact holes is formed.

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  2. Contact hole etching

  Using the contact hole resist pattern as a mask, contact holes are formed in the dielectric film by performing etching treatment. After etching, the resist pattern is removed. These holes are extremely small and deep (high aspect ratio), and thus great care must be taken to control hole diameter and depth.

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  3. Plug-tungsten filling

  A tungsten film is formed on the silicon wafer surface using the CVD method, and the contact holes are filled.

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  4. Plug-tungsten polishing

  The surface is polished and excess tungsten film is removed. Tungsten is left only in the contact holes.